General purpose programmable logic chips that are available as off-the-shelf components (i.e., are commercially available) are generally not custom designed for special applications such as logic emulation, prototyping and computing. Examples of a general purpose programmable logic chips are field programmable gate arrays ("FPGAs"), programmable logic arrays ("PLAs"), and programmable array logic ("PALs"). General-purpose programmable logic chips have served adequately in the initial development of applications such as hardware logic emulation, prototyping and computing. However, in these applications, general-purpose logic chips have some drawbacks. Many general-purpose logic chips emphasize speed and density (i.e., how many logic gates can be implemented in a single chip) above other goals. To be cost effective for most applications, a general-purpose programmable logic architecture should provide routing resources sufficient to give a good chance of fitting a design therein and allowing the use of most of the available logic gates in the integrated circuit. However, with a general-purpose programmable logic architecture, there is always a possibility that a given design or partition may not be implementable, even though the gate count (i.e., the number of gates that the manufacturer of the programmable logic chip claims the chip can implement) is within the rated capacity of the chip. Also, the speed of the compile process is of lesser importance in the general purpose logic chip.
In contrast, in a logic emulation, prototyping or computing application, the priorities are different. The logic chip is normally part of a larger, multi-chip system, often with tens or hundreds of logic chips. Large input design netlists must be automatically compiled into all these logic chips with a very high degree of success and a minimum of user intervention. A netlist is a description of a logic design that specifies the components of the design (e.g., the logic gates) and how the components are interconnected. Each "net" of a netlist defines a circuit path between pins on a component or an input/output pad. It is essential that the logic chip used in these applications provide routing resources which are flexible and capable enough to nearly always succeed in allowing most of the logic resources to be used by a filly automatic compile process. This compile process should execute rapidly. Fast compile times minimize the time required to get from the time the user's design is presented to the emulator system to the time all the logic chips are programmed and ready to run the user's design (i.e., emulate the user's design).
The differences between the goals of the general purpose logic chip and the goals of a logic chip used in emulation, prototyping and computing applications present a situation where there is a need for a logic chip which is specialized for logic emulation, prototyping and computing applications.